Integrated circuitry may include arrays of memory devices for data storage. The memory devices may, for example, be dynamic random access memory (DRAM) devices; with the DRAM unit cells corresponding to transistors coupled with charge storage devices (typically capacitors). Alternatively, the memory devices may lack the capacitors of DRAM. Such memory may be referred to as zero-capacitor-one-transistor (0C1T) memory, and may correspond to so-called ZRAM™ (zero capacitance DRAM).
A continuing goal of integrated circuit fabrication is to increase the level of integration; with a corresponding goal to decrease the size of memory devices, to simplify memory devices, and/or to reduce the complexity and amount of wiring associated with memory devices. Another continuing goal of integrated circuit fabrication is to reduce the number of steps of a fabrication process, thereby improving throughput and possibly reducing costs.
One approach being utilized to increase integration is to incorporate partially-insulated transistors into memory devices. More specifically, the approach is to utilize partial semiconductor on insulator (SOI) to alleviate leakage at source/drain junctions of transistor devices. The individual transistor devices comprise a gate, and a pair of source/drain regions on opposing sides of the gate. The source/drain regions extend within a first semiconductor material, and have insulator directly beneath them which isolates them from a bulk semiconductor material beneath the first semiconductor material. The insulator provided beneath the source/drain regions does not extend under the transistor gate to any substantial degree.
It is desired to develop improved memory devices, and improved methods for fabricating memory devices. Although some embodiments disclosed herein were motivated, at least in part, by such a desire, other embodiments may have applications beyond memory device structures and fabrication.